Camera and Display subsystem, Memory subsystem, Memory Management, ARM Architecture

Capabilities and Experience:

• Bachelor’s degree in Electrical Engineering or Computer Science with 5+ years of relevant experience, with minimum 3+ years in silicon
  validation
• Silicon Validation experience, developing stress test plans and content, silicon validation frameworks or related infrastructure, debugging skills.
• Experience in validating hardware features for SOC (display system, memory subsystem, memory management)
• Familiarity with ARM CPU Architecture Caching and Coherency protocols knowledge
• Performance Validation Experience
• Expertise in Security protocols and architecture e.g., – IOMMU, Access control, Encryption etc.
• Firmware Development
• Strong knowledge of OS Fundamentals, Multi-threaded embedded programming
• Experience in Bare Metal testing.
• Validation experience of protocols using software on chip blocks, specifically camera, CSI PHY, ISP, display protocols DSI and DP
• Pre and Post Silicon SoC level expertise on data-chains, DMAs, fabric etc.
• Proficiency in JTAG Debugger languages- Lauterbach PRACTICE with experience of debugging complex systems and performance  bottlenecks.
• Ability to measure various analog parameters in the lab with highspeed oscilloscopes and other lab equipment. 
• Ability to write and execute memory related tests to establish functional health of our SoCs on silicon, both under normal and PVT conditions.
• Good understanding of validation fundamentals.
• Solid understanding of emulation technologies.
• Familiarity with emulators and waveform-based debugs.
• Programming Skills- Assembly, mixed assembly programming, C, C++
• Scripting – Python, shell scripting
• Microsoft excel tools for report generation /graphs.

Responsiblities:

• Building emulation models, running, and debugging test cases, resolving environment issues, and driving emulation and acceleration capabilities for pre- and  post- silicon validation in platforms like Synopsys Zebu or Cadence Palladium
• Drive report generation, analysis of memory margins across PVT
• Drive the post silicon bring up and validation activities for the DRAM.
• Execute the DRAM validation, margin data collection, stress testing across PVT.
• Team player and a mentor who is self-driven, motivated.
• Responsible for quality and timeliness of the team output