Join Mettlesemi’s DFT design team to develop next-gen chips with a revolutionary architecture.
Contribute to a multifaceted DFT approach, including architecture definition, logic design, verification, test pattern generation, and chip bring-up.
Work in a dynamic, open, and fast-paced environment on cutting-edge silicon chip technologies.
Shape the future of chips for top-notch clients.

Senior DFT Engineer pivotal in device lifecycle, from definition to mass production.
Collaborate with VLSI groups (chip design, verification, backend, test, and reliability).
Develop, implement, and verify DFT on complex SOCS.
Work closely with architecture team for DFT understanding.
Ensure DFT design rules compliance with design teams.
Collaborate with physical design team to meet DFT requirements.
Expertise in SOC-level DFT techniques (ATPG, MBIST, JTAG, boundary scan).

6+ years chip design experience.
4+ years as a DFT engineer in a semiconductor company.
Bachelor’s/Master’s in Electrical/Electronics Engineering.
Strong post-silicon DFT bring-up and debug experience.
Hands-on experience with multi-vendor DFT tools.
Proficiency in ATPG tools (Mentor TK).
Exposure to static timing analysis; timing closure.
Excellent scripting skills in Perl/Tcl/Tk/Python.
Knowledge of DFT technologies (JTAG, MBIST, Scan).
Experience with RTL Coding (Verilog, System Verilog, VHDL).

Expertise in DFT methodologies (scan insertion, scan compression, boundary scan, memory BIST).
Experience with DFT tools (Tessent, ATPG, MBIST, JTAG).
Proficiency in Shell/Perl/Tcl and other scripting languages.
Familiarity with ATE.
Chip design, Verilog, and System Verilog. Verification, UVM methodology.
ATPG tools, scan insertion tools, gate-level simulations. Static timing analysis. Scripting (Perl/Tcl).

DFT ENGINEER

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