UART Peripheral Verification with UVM Framework

UART Peripheral Verification with UVM Framework

The UVM Framework is an open-source package that provides a reusable UVM methodology and code generator that provides rapid testbench generation.

It delivers an open, unified class library and methodology for interoperable VIP and eliminates need for interoperability among multiple verification libraries. It is based on a base-class library proven in thousands of projects and provides built-in automation and testbench capabilities. It supports module-to-system and project-to-project reuse and Incorporates the collective verification knowledge of Accellera members and it runs on any simulator supporting the IEEE 1800 standard. It enables multi-language plug-and-play VIP and includes a methodology user guide and reference documentation and it integrates with the proven metric-driven verification.

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