SystemVerilog Based Verification of SPI Slave

SystemVerilog Based Verification of SPI Slave

The VIPs are built on Industry Standard UVM based environment and these industry standard VIPs are used as golden reference. Protocol checks for SPI and AXI4-Lite bus interconnect in the controller IPs are checked for compliance and scoreboarding of different checks are done through the golden reference in the framework.

DUT is the SPI Slave, the AXI4-lite interface of the DUT is paired with AXI4-lite VIP; the latter will Master the AXI bus. The SPI interface of DUT is paired to a SPI VIP which will act as Master to the SPI bus.The SPI VIP can be used in generic/normal mode or device mode; For our testing purpose the SPI VIP is used in generic mode. DUT Registers are configured via dedicated tasks which are based on AXI write-read calls; Register config tasks are run on the AXI4-lite VIP. Appropriate & relevant combination of DUT Register config tasks, SPI VIP tasks & some miscellaneous code make up the test cases.

Supported transfer sizes for AXI4-lite are 32-bit or 64-bit only. But the DUT has register sizes ranging from 8-bit, 16-bit & 32-bit hence addressing 8-bit & 16-bit registers isn’t possible. The AXI4-lite VIP has a non-compliance mode wherein 8-bit & 16-bit transfer sizes can be accomodated. To successfully address all the registers of the DUT, AXI4-lite VIP is used in non-compliance mode

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