Mettlesemi at Siemens User2User Verification Forum 2026
Mettlesemi Systems and Technologies Private Limited was pleased to take part in the Siemens User2User Verification Forum 2026 India, where we presented our work on the efficient FPGA design and verification of an Ultra Low Latency (ULL) High Frequency Trading (HFT) platform using Siemens Questa tools.
At the heart of our work was a high performance hardware platform designed to achieve deterministic ultra low latency, featuring parallel pre trade validations through a high speed Risk Management System (RMS), AES GCM and MD5 security engines operating within single digit clock cycle latency, and an optimised tick to trade flow for throughput and deterministic execution. The implementation was supported by a transaction centric UVM based verification environment for complex RTL systems, mixed language integration using VHDL and SystemVerilog with PCIe and Ethernet interfaces, and a unified debug and verification workflow using Siemens QuestaSim and Visualiser. SystemVerilog DPI integration with C models and automated regression further supported accelerated validation and workflow management.
This work reflects Mettlesemi’s capabilities in FPGA design, RTL verification, ASIC design, hardware acceleration, and high-performance computing for mission critical, latency sensitive applications. It also reinforced the value of a unified verification flow and advanced debug tools in accelerating the development of complex hardware systems.
We thank the organisers of the Siemens User2User Verification Forum 2026 India, and everyone we interacted with at the forum. Special thanks to Bishwanta Singh L and Rohan S from Trident Tech Labs Ltd. for their support with the Siemens tool flow.