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• Create Date April, 2025
• Last Updated May, 2025

ULL PCIe DMA Controller

The ULL PCIe DMA Controller implements bidirectional data transfer between the host CPU and FPGA through a PCIe interface with a round- trip time of 615ns. This IP core features multiple build time parameters, allowing the users to efficiently design their applications while maximizing resource utilization without compromising latency performances.

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